The world of electronics is an ever-shrinking world. The physical space needed and/or allocated to implement a given function is getting smaller and smaller. The use of dual-sided, multi-layer printed circuit boards with miniature surface mount technology (SMT) components and custom application-specific integrated circuits (ASICs) installed thereon to form small, compact, printed circuit assemblies is now common. The spacing between the pins of components becomes smaller as the designs are made to fit into smaller physical configurations. The physical spacing, such as pin spacing and wire trace spacing, is further reduced when the assembly is intended to be portable, such as a modem designed to support the Personal Computer Memory Card International Association (PCMCIA) standard.
In the context of such a crowded and densely populated printed circuit assembly, it is often difficult to determine if an electronic device or component has been installed correctly. More particularly stated, it is often difficult to determine the integrity of an electrical connection between the wire traces of the PCB and the pins or leads of the installed device or component.
One method of testing a printed circuit assembly involves use of a "bed of nails" test fixture with a conventional in-circuit tester, such as an HP 3070 Board Tester manufactured and distributed by the Hewlett-Packard Company of Palo Alto, California. The bed of nails test fixture provides a number of contact probes for accessing points on the printed circuit assembly. There must be contact between the probes of the fixture and a device on the printed circuit assembly or signal paths on the printed circuit assembly (typically via a conventional test point access node) for the test method to work. The method is often called a "bed of nails" testing method because the probes are typically sharp metal contact probes configured so that the printed circuit assembly can be placed on the "bed of nails" and tested. In this manner, the probes touch or access various parts of the device or the signal paths on the printed circuit assembly (via the test point access nodes on the printed circuit assembly) and thereby allow measurements to be made on the device.
Typically, the device is stimulated through signals provided through the probes. Measurements from the probes are then compared to "correct" values to determined if the device on the printed circuit assembly is defective. However, the appropriate signal path must be in physical contact with the test probes for this testing method to work. Densely populated printed circuit assemblies often have inaccessible signal paths, such as wire traces beneath multiple layers on the printed circuit board assembly, thereby hampering the use of such a "bed of nails" test fixture. Therefore, "bed of nails" test fixtures are often ineffective when attempting to test a densely populated printed circuit assembly.
Those skilled in the art will be familiar with Boundary Scan, which is another test method for determining if a device is defective. Boundary Scan (illustrated in FIG. 1 as prior art and also known as IEEE 1149.1 or Joint Test Action Group (JTAG)) is a specialized non-contact test method for testing the board-level interconnections among devices on a printed circuit assembly. More particularly, Boundary Scan is a special form of conventional scan path testing that is implemented around every input/output pin of a device in order to provide controllability and observability of the input/output pin values during testing.
Referring now to FIG. 1, the Boundary Scan method generally uses a set of four pins 110a, 110b for each device 115a, 115b. These pins allow an in-circuit tester (not shown) to gain access to all of the pins on the device 115a, 115b. The in-circuit tester (not shown) typically sends commands to a boundary scan port 105a within the device 115a in order to read or control the input pins and the output pins on the device 115a. Those skilled in the art will realize that while the boundary scan port 105a is typically implemented within the circuitry of the device 115a, the boundary scan port 105a may also be implemented as a separate circuit. FIG. 1 merely shows the boundary scan ports 105a, 105bimplemented within the circuitry of the devices 115a, 115b in order to avoid confusion.
Boundary Scan is most advantageous when a printed circuit assembly 100 has several interconnected devices 15a, 115b which implement it. This is advantageous because it is then possible to use, for example, port 105a, to generate an output on one pin 120a and read it from a connected pin 120b on another device 115b via, for example, port 105b, without having physical access to either of the pins 120a, 120b or the signal path 125 between the pins 120a, 120b. This is particularly advantageous because the same pins and signal paths which are used for Boundary Scan testing are later used to create the normal function of the circuit during normal operation. The term "normal operation" is used to describe the operation of the completed circuit assembly by the consumer or end user in the manner intended by the designer.
The digital version of Boundary Scan is more formally defined by the Institute of Electrical and Electronics Engineers, Inc. (IEEE) and the published IEEE standard 1149.1 (1990). The analog version of Boundary Scan is more currently being defined as IEEE 1149.4 (1997). Additional information regarding Boundary Scan is available by referring to the published IEEE 1149.1 standard, which is available from IEEE, Inc., New York, N.Y. Furthermore, while still not in a final form, information regarding the preliminary IEEE 1149.4 Boundary Scan standard is also available from IEEE, Inc., New York, N.Y.
While Boundary Scan testing allows testing of interconnected devices without accessing the pins of the interconnected devices, one skilled in the art will appreciate that such testing is not useful in all situations. For example, Boundary Scan testing is less useful where there is only one device implementing Boundary Scan and that device is surrounded by devices that do not implement or support Boundary Scan testing. In such a situation, it is often necessary to access many of the pins or signal paths on the printed circuit assembly with a probe. Thus, it may still be difficult to test the integrity of connections of a device on a populated printed circuit assembly using Boundary Scan.
Another non-contact testing method for testing the integrity of a device's connections is capacitive testing. An example of such capacitive testing is described in U.S. Pat. No. 5,254,953 (hereinafter "the '953 patent") entitled "Identification of Pin-Open Faults by Capacitively Coupling Through the Integrated Circuit Package" and assigned to the Hewlett-Packard Company of Palo Alto, Calif. In the '953 patent, a system is described for determining whether pins of a device are properly soldered to a printed circuit board assembly. FIG. 2 illustrates such a prior art system.
Referring now to FIG. 2, a printed circuit assembly 200 has an integrated circuit device 205 mounted to a printed circuit board 210. A capacitive sensor 215 is positioned over the device 205 while a test probe 220 contacts a pin under test 225 via a pad 226 and a connection 222 between the pin 225 and the pad 226.
In a capacitive testing process disclosed in the '953 patent, the test probe 220 typically injects an alternating current (AC) test signal (such as a 10 kHz signal at 0.2 volts) into the pad 226 connected to the pin under test 225. The capacitive sensor 215 then detects this test signal via the capacitive coupling between the pin 225 and the bottom of the capacitive sensor 215 and converts the AC signal to an intermediate signal called a detection signal. The value of the detection signal is proportional to the detected amplitude of the AC signal. In this manner, the value of the detection signal from the capacitive sensor 215 may be compared to a threshold value to determine characteristics about the detected AC signal (such as the strength of the AC signal). If the electrical connection 222 between the test probe 220, the pad 226, and the pin under test 225 is open, the value of the detection signal will be much smaller than anticipated. An in-circuit tester (not shown) connected to the capacitive sensor 215 then indicates that the printed circuit assembly 200 has failed the test and declares that the pin under test 225 is open.
While the capacitive testing process described in the '953 patent allows testing to detect open pins on populated printed circuit boards, a test probe is still required to provide the test signal. Moreover, test probe access to the pin under test must still be available for capacitive testing as described in the '953 patent to work. Such a capacitive testing process would be ineffective in a circuit assembly where test probe access to the pin under test is not available, such as a densely populated circuit assembly where the pin spacing and wire trace spacing are extremely small.
In summary, for testing the integrity of a pin of a device mounted on a populated printed circuit assembly, there is a need for a system that: (1) improves the capacitive testing method to allow testing of the integrity of the connection between the signal path and the pin without physically probing the pin; (2) allows testing without probing a signal path connected to the pin; (3) reduces the required number of test point access nodes on the printed circuit assembly; and (4) allows testing of a device's pins where there is only one device on the printed circuit assembly implementing Boundary Scan or where a Boundary Scan device is surrounded by other devices that do not implement or support Boundary Scan testing.